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HP 1661CS 100MHz State/500MHz 102ch Timing Logic Analyzer
SOLD OUT sold |
log180 |
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Logic Analysis;
State and Timing channel:102,
Timing Analysys:250MHz all ch(Conventional),500MHz half ch,
State Analysis speed:100MHz(All ch),
State Clocks/Qualifiers:6,
Memory depth:4k/ch,8k in half ch mode,
Oscilloscope;
Channel:2,Max Sampling Speed:1GS/s/ch,
Bandwidth:DC-250MHz,
Vertical Resolution:8bits,
Memory depth:8k sample,
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J-Manual*1
POD:6,Graber:110,Grand lead(short):8,Double Probe Adapter:1,
Soft case, |
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